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| Design, Analysis And Optimization Of Monolithic Inductors For RF Applications |
| (Diana Pukneva, Gergana Dodeva, Marin Hristov)
| The main purpose of the work is to create a library of monolithic spiral inductors, which can be used as standard cells in RF applications, such as Power Amplifiers, VCOs, Low-noise Amplifiers etc.
The research in this project is focused on monolithic inductors and the effect of the inductor-Q on the performance of RF building blocks. A custom computer-aided-design tool called ASITIC (Analysis and Simulation of Inductors and Transformers for Integrated Circuits) is used for the design, analysis and optimization. Created in ASITIC structures are verified with simulations in CADENCE. Pi model is used to represent the two-port parameters of the structure at a particular frequency. From two-port measurement results generated in ASITIC, low-order, frequency-independent lumped circuits are used to model the physical behavior over a broad frequency range. The analysis is applied to traditional square and polygon inductors as well as to multilayer metal structures.
Integrated inductors with inductances of 1-20nH are designed, analyzed and optimized for the following processes - AMS CMOS 0.35µm and AMS BiCMOS SiGe 0.8µm. |
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| Artificial Neural Matrix of Analog Neurons Implemented On Standard CMOS Technology |
| (Momchil Milev) |
The project concludes a series of findings on the research and design of an artificial neuron model implemented in a conventional CMOS fabrication technology. Shown is the design of the individual elements building the artificial neuron-one or more synapse(s), a summing node and a hard-limiting output stage. The attention is focused on the particular choice of these elements, on the approach for the design solution and to the operation of the neuron in a system of interconnected neurons - artificial neural network (ANN). A list of desired properties of the hardware model is derived from this discussion which then is used to form the requirements for the design.
First, the design requirements and model for the synapse is considered. The motivation not to use floating-gate devices in modeling of the synapse connection is explained. Non-linear relationship in the synapse function due to the specific implementation is briefly discussed. The report references previous reports to avoid lengthy circuit description. After presenting synapse modeling, a circuit for an analog neuron is shown.
Second, the input-current conversion of the input pre-synaptic signal is discussed. Method to decrease input-current conversion and processing time is described which uses input-current capacitor pre-charging.
Third, method of storing synapse weight is discussed. A mixed digital-analog approach for weight storage is suggested. Information on the weight dynamic range and resolution is given. Weight charge degradation due to leakage current is considered and a method for compensation is suggested. Special design of weight- and input-current switches is discussed.
Last, a complete system-on-a-chip (SOC), based on the proposed analog neuron design, used for fingerprint image feature extraction is shown. System operation is briefly discussed and some physical silicon data is considered in support of the idea that the limiting factor in building ANN is the digital circuitry while the analog artificial neuron's allow high scale of integration.
Index terms - Artificial Neural Networks (ANNs), analog synapse model, ANN implementations, CMOS. |
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| Monolithic RF Power Class DE Inverter |
| (Plamen Popov, Nikola Dinkov, Gergana Dodeva, Cristy Mihailova ) |
Signal amplification is a fundamental function of the radio portion in all wireless communication systems. The transmitted signal level must be amplified sufficiently so that despite loss inherent in wireless transmission, the signal can be received by a nearby base station.
The circuit of the inverter class DE is shown in fig.1. Its purpose is to ensure specific output voltage and power due to the input signal variation, which controls the switching transistors.
In this project electrical and topological design of the inverter class DE and the drivers are presented. The inverter operates with 25% and 50% duty cycle of the input signal. The driver stages for inverter control are also presented. They have to provide pulses with minimum slope.
The basic problem at the inverters class DE development is to realize drivers with low consumption and inductors with high Q factor at high frequencies.
At first the circuits are explored at low frequencies (1MHz) using program Orcad 9.2 with purpose to get familiar and to investigate their operating regimes. In this paper the results from inverter and drivers PCB realization at 1MHz are also shown.
The inverter is designed to operate at high frequency (1GHz) using CAD system CADENCE. The electrical simulations and physical designs of the circuits are made for AMS 0.8um SiGe BiCMOS and AMS 0.35um Si CMOS technologies. The operating regime is set using transient analyze at power supply voltage Vdd=2.8V. The inverter is investigated in respect of harmonic distortion, noise and temperature. The goal of PA is to achieve maximum efficiency for 10 dBm output power at 1GHz and current consumption approximately 10mA.
The driver has differential input with sinusoidal signal Vp-p=1V at 1GHz. The maximum amplitude of the driver output pulses is near to power supply voltage. |
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| A 1GHz, 10DBM Class E Power Amplifier |
| (Olga Antonova, Gergana Dodeva, Marin Hristov) |
The basic class E circuit includes a transistor, which is connected with a RFC to the supply voltage and to the load network. The load network is made up of a capacitor C shunting the transistor and a series tuned L1C2 resonant circuit. The transistor is driven hard enough to act like a switch. The principle of class E power amplifiers is to avoid by design the simultaneous existence of high voltage and big current in the switch, even in the case of a long switching time. That implies 100% efficient conversion of dc to RF energy. The most important advantages of class E amplifier is: the small number of circuit components; it provides maximum available output power; harmonic distortions can be decreased to an acceptable values by proper choice of the elements.
In this project is investigated the electrical design of the circuit and the layout of class E power amplifier. To be determined the most proper working regime it is made electrical analysis of the circuit and its behavior is researched at lower frequencies (5MHz) by using PSpice. Before analyzing the class E power stage at 1GHz there are made detailed researches of the circuit components - active and passive - to obtain à view for their characteristics. The power amplifier is researched at 1GHz by using the CAD system CADENCE.
Class E power amplifier is analyzed with 50% and 25% duty cycle of the input driving pulse- signal. There are compared the results reached by designing the power amplifier for two technologies: AMS 0.8µm SiGe BiCMOS and AMS 0.35µm Si CMOS. The stage is also analyzed in respect of the noise, temperature and harmonic distortion.
After designing the layout of the circuit, which achieves the best efficiency for 10dBm output power, it is made resimulation. The last one associates the parasitic elements. Optimization of the class Å power amplifier includes change in placement of the components for optimization of the connections and therefore smaller parasitic elements. Another aspect of the improvement can be the use of smaller capacitors, because monolithic inductors and connections introduce complementary capacitances. Mentioned above in this paragraph imposes electrical design of the power amplifier to be for bigger then 10dBm output power to obtain the desired output power after the layout resimulation. |
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| Analog Transmitting Modules For Wireless Communications |
| (Kristi Mihajlova, Gergana Dodeva, Marin Hristov) |
The basic block in the contemporary wireless communications is a transceiver system. The main purpose of the transmitter section is to modulate, convert and amplify the RF signals. The transmitter development is a challenge because there are a few similar architectures up to now. It must ensure low noise, low power dissipation, band selectivity and etc.
This project describes the building blocks design of transmitter such as low-noise biasing (LNB) and power amplifier (PA).
The LNB circuit provides stable voltage in the presence of temperature, load and power supply variations and current for VCO controlling.
The power amplifier ensures high enough output signal with low harmonic distortions. Two classes of PA are investigated: class E Amplifier and class DE Inverter. The small number of circuit components of class E PA make its control easier - only one transistor, but the presence of two inductors decreases its performances: efficiency, current consumption and output power. Conversely, the class DE inverter ensures higher efficiency and lower losses because there is one inductor in the circuit. The control is complicated due to the availability of two switching transistors.
The monolithic inductors for 1GHz are developed. The program ASITIC (Analysis and Simulation of Inductors and Transformers for Integrated Circuits) is used for the design, analysis and optimization. Created in ASITIC structures are verified with simulations in CAD system CADENCE.
The circuits electrical and topology design at 1GHz are investigated and some of them are realized in AMS 0.8um BiCMOS SiGe and AMS 0.35um CMOS Si technologies using CAD system CADENCE.
The voltage-controlled oscillator (VCO) and drivers for the PA are in a design processing. |
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| Sinusoidal PWM System |
| (Peter Goranov, Marin Hristov, Mariana Goranova, Anthony Trifonov) |
A sinusoidal PWM system has been designed where the modulation ratio is varied. The PWM signals are used in a wide
variety of industrial and commercial applications of sinusoidal PWM inverters such as asynchronous motor drives and
uninterruptible power supplies (UPS).
The modelling and simulation processes are performed using high technologies and the software systems SYNOPSYS and
Altera Max+PlusII involving the typical main steps: system entry, validation, implementation and verification. As
physical representation the team has used FPGA matrices. This approach of digital design leads to the fastest
results receiving and system prototyping. Since our system has a specific application the FPGA Design may be
considered as a final stage just before implementation into a programmable matrix. In this case we used to implement
into the Altera's FPGAs as EPF10K10 with fastest speed grade.
The synthesis of a ready RTL VHDL code is through the Altera software using MAX+PlusII synthesizer and optimizer.
After successive compilation into the FPGA a VHDL netlist is produced ready for re-simulation in SYNOPSYS or ALTERA
MAX+PlusII. Good results from the simulation largely guarantee non-problematic device work.
The main advantage in the modelling process using the SYNOPSYS Design System and implementation into the FPGA
matrices is a great possibility for design reuse, very short time starting from specification down to the
implementation and significant flexibility in system adjusting stage. Thus the design does not require big teams and
reduces investments. Moreover the optimised gate-level description, produced according to a target library, is
automatically converted to a layout using a silicon compiler.
The simulation results prove the correct idea for obtaining controlled sinusoidal PWM signals for power electronic
applications. |
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| BiCMOS Integrated Circuit for a Phase Control |
| (Momchil Milev, Peter Goranov, Marin Hristov, Mariana Goranova) |
A power and high-voltage semicustom IC for a phase control of thyristor converters and line-frequency rectifiers has
been designed using the complex MADE for a HBiMOS 2m technology of Alcatel-Mietec. The MADE complex is coupled to a
complete suite of powerful electrical and physical design tools developed by Analog Artist of Cadence Design System.
The high-voltage bipolar-MOS technology HBiMOS enables us to use 30V supply voltage for the analog cells and 15V for
the digital cells, respectively, with high gate voltages (>18V). This high supply voltage enforces a full custom
design of 2-input NAND and NOR gates, and an inverter.
After the circuit has been designed, simulated, checked, and the test vectors are generated, the topological design
was performed using the tool Cell Ensemble of Cadence. After placement and routing, layout-vs.-schematic (LVS) and
design-rule checks (DRC) were completed. Following a successful post-layout simulation, masks are made, and
prototypes are fabricated through the EUROPRACTICE. Finally the prototypes are verified. The provided test of the
prototypes shows that all specifications are met and proves our ideas quickly and easily. |
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| Precise CMOS Operational Amplifier |
| (Marin Hristov, Minka Gospodinova, Ognian Marinov, Rossen Radonov, Boyanka Nikolova) |
| A relative simple schematics of CMOS test OpAmp is developed with good features for gain (>30 000), bandwidth (>4MHz) and especially for CMRR (26dB greater than the gain). These values for CMRR are achieved, using crossed transistors in the input differential stage, where, furthermore, the offset is reduced, using parallel transistors. The bandwidth is guaranteed by the two stage structure of the OpAmp. The output stage is rail-to-rail and works in AB class with relative small output resistance and nonlinearity. Because of the investigation purpose of the test OpAmp the reference current mirrors of the input and the output stages are different. In addition external components is possible to be connected and a variety of circuits could be made. This development is supported by TH-620/96 and INCO Copernicus SITIC Project 960170. |
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| Digital Sound Playing IC |
| (Rossen Radonov, Georgi Dimitrov, Vladimir Dragiev) |
| The type of IC is digital-analog. Its application is to play digital sound stored in external memory. The sound has to be transformed to digital format.
The IC has been designed using the software package CADENCE and the 2 micrometer CMOS technology of ALCATEL. The IC comprises pulse oscillator the frequency of which
can be controlled from the outside of the IC, 20-bit counter which addresses the outer memory and is being clocked by the pulse oscillator and 8-bit digital-to-analog converter. The IC has 2 control digital input pins, 4 digital input pins for loading of the 4 most significant bits of the counter, 8 digital data input pins, 3 analog input pins for pulse frequency control, 20
digital output pins for memory addressing, and an analog out pin from the digital-to-analog converter. The digital-to-analog converter comprises a R-2R resistor array and
an opamp. The power supply is +/- 5V. |
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| Mixed Signal Circuit for Educational Purposes |
| (Ivan Kutzarov, Stanislav Darakchiev) |
| This is a mixed analog-digital circuit for experimental use in educational process. It allows examination of the available library elements and further design system
development. The IC involves analog, digital and analog-digital blocks which can be used separately or in combination. There are two ADCs, based on the method of successive approximation. One of them is user designed and another is a standard library cell. ADCs can be used for voltage measurements within range 0-2.55V. Both results can be compared and the conversion accuracy estimation can be made. The data received by the ADCs is expected to be shown on a 3 digit LED display with a dynamic indication. Driving logic for display is
synthesized by means of the Hardware Description Language VHDL and the SYNOPSYS software. Several sensors based on PN junctions are placed in the
chip. Temperature and/or frequency analysis of almost all blocks is possible. |
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| CCLFRITC |
| (Mariana Goranova, Gergana Tancheva) |
| A control circuit for linear-frequency rectifiers, inverters, and thyristor converters(CCLFRITC) has been designed. CCLFRITC provides phase-shifted firing pulses
in two channels for the positive and the negative half-cycle, which are suitable for linear-frequency rectifiers, inverters and AC regulators. The gate signals
delay is determined by control signal with respect to zero crossing of the AC linear-frequency voltage. The control circuit has an additional input in order to
prohibit the firing pulses in case of overload or overvoltage operation. The design process is performed using the CADENCE Analog Artist Design System and the
MIETEC 2.4um technology file. |
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| Project EURO 178-4009.1 Multiplier-Accumulator |
| (Vassili Tchoumatchenko, Tania Vassileva) |
Description
The MAC06 circuit is a standard cell based multiplier-accumulator, which consist of 16 x 16
bit-multiplier, 32 x 48 bit adder, six 48-bit accumulators and control logic. The circuit have
eight bi-directional data pins, five address inputs and seven control pins. This simple interface
specification allows MAC06 to be used as a coprocessor for a low cost microcontrollers. One
possible application is a high-precision, digital, laboratory power meter.
Implementation
CADENCE Opus with ES2 1mm design kit were used for chip standard cell implementation. Physical realization of the circuit requires approximately 12200 transistors plus 16x16 bit
multiplier megacell. Overall chip size is 13,135 square millimeters using 28-pins DIL package.
Performance and test results
One "multiply-add-store" cycle can be initiated every 100 ns.
The chips produced is currently under test at Sigma Delta Corporation/ Bulgaria. |
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| Project EURO 157-4009.01 Bit-Sequential Multiplier |
| (Tania Vassileva, Vassili Tchoumatchenko) |
Description
Multiplier is based on Chen and Willoner's algorithm. This multiplier operates in time O(n),
where n is the lengths of the multiplier and multiplicand, both of which are fixed point, expressed in binary notation. Multiplier inputs one bit of multiplier and one bit of multiplicand at
each time step and outputs one bit of product at each time step after the first. It requires n
identical modules and have only nearest neighbor interconnections.
Implementation
Using FPGA multiplier as a prototype, a standard cell was implemented.
CADENCE Opus with ES2 1mm design kit were used for multiplier's standard cell implementation.
Physical realization of the multiplier circuit requires 901 standard cells. The necessary core area is 1,67 square millimeters with aspect ratio of 1,15. CADENCE Sinergy Optimizer is used to improve design performances in terms of speed and die size. The benefits are
an decreased number of cells used (within 44%) as well as reducing of core area with 43%
compared to non-optimized version.
Performance and test results
According logic simulation the multiplier works with 120 MHz clock speed without timing
violations.
Functional test of the chips produced was made at Sigma Delta Corporation/ Bulgaria. The
test results proof multiplier proper functionality.
Related papers
1. Tchoumatchenko V., V.Zahariev, T. Vassileva, FPGA Implementation of a Bit-Serial Multiplier, The
European Design and Test Conference ED&TC 1995, p. 49-52, March 1995
2. Vassileva T., V.Tchoumatchenko, FPGA Design Migration: Some Remarks FPL'96, Sixth International
Workshop on Field Programmable Logic and Application, September 23-25, 1996, Darmstadt, Germany |
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Analog Design