|Development Of Baseband And LMP Layers In Bluetooth For General Purpose In Fuzzy Logic Devices|
| (Ilian Kostov, Blagomir Donchev)|
|This project describes the design of the digital Baseband and LMP layers from hardware development aspect related to generic core for Fuzzy Logic devices. The Baseband layer performs the functions related to interface interaction between Bluetooth chipset and external or integrated radio chip and a host system. In Baseband are integrated different modules for data processing like module for generating frequency hopping sequence, fast error correction codes 1/3 and 2/3, cyclic redundancy check algorithm, whitening, assembling and de-assembling of data packets. All these modules are successfully developed and implemented in designed device. In addition some hardware optimizations have been made to meet the requirements of modern electronics.
The LMP layer is responsible for all control messages exchanged in a Bluetooth network. These control messages are used for link set-up, security and control. The messages are filtered out and interpreted by LMP on the receiving side and are not propagated to higher layers. In the module examined in current paper are implemented all basic and mandatory control messages' responses and the generation of them.|
By the reason of a higher degree of design abstraction, the development of the module has been done with hardware description language - VHDL. For verifying his functionality the designed module has been simulated and synthesized for Virtexe FPGA platform. During development of Bluetooth module is integrated new complex architecture, which support its low cost upgrade related to new generations of Bluetooth devices. The design has been provided with generic microprocessor interface for easy adaptation in Bluetooth systems. The radio interface has been done with fully support of standard BlueRF, defined from Ericsson.
|Design Of System For Satellite Identification|
|(Blagomir Donchev, Yana Krasteva, Marin Hristov)|
|The system was designed to be integrated in digital devices such as satellite receiver, set-top-boxes, multimedia home platforms, etc.|
The goal of the designed system is to recognize with witch satellite a communication channel is being hold. For this aim, the system, according to a work algorithm pulls out predefined data fields for a transition bit stream and saves it in internal latch memory. One of the futures of the system is that it supports standard communication interface to a microcontroller and tuner decoder as well as tri state outputs for data buss connection
The module totally supports The European standard for data over satellite's channels DVB (Digital Video Broadcast) and the MPEG2 (ISO-13818-1) system layer used by DVB like data transfer protocol.
The chosen design method was a "Top-down" design flow. Following that steps we started with the developing of a functional block diagram, and then each component of the system was behaviorally described by using a high-level description language VHDL.
For implementation was used software ISE 4.1 from XILINX.
The design was tested by behavioral and real simulation and for hardware implementation a chip SPARTAN II (XC2S100-5PQ208C) from XILINX was chosen.
This design was made in conjunction with an industrial partner and was tested in real environment.
|Design Of OFDM Based Wireless Network Modules|
|(Dobromir Arabadziev, Blagomir Donchev)|
|This project presents the design of a modulation/demodulation unit for QAM signals. It consists of two modules which are parts of the physical layer of the IEEE standard 802.11a for data exchange through radio signals.|
The modulator was designed by means of a hardware description language (VHDL).Using a "top-down" method, we reduced considerably the developing time.
The demodulator is made of two parts: a phase and amplitude correction module and a decision device. We developed a correction algorithm based on the pilot signals that are transmitted together with the data symbols according to the standard.
The decision device works on the principle of minimal Euclidean distance between the received signal and the constellation points. Our algorithm is fast and uses minimal resources. To prove the mathematical model, we wrote a MATLAB program and simulated the system under various modes of modulation and various levels and forms of noise and phase distortion. The BER observed was close to the theoretical one.
Based on this efficient mathematical model and using a "top-down" design method, the functional algorithms were described in VHDL. By means of the SYNOPSYS CAD system, the behavioral level of abstraction was translated into logical structure level and then physically implemented on FPGA.
|Design Of SDI Controller|
| The current implementation is for 625-line PAL component digital video signal based on the 4:2:2 sampling scheme. The transmission speed is 270Mb/s. The module is made using Field Programmable Gate Array (FPGA) platform from Xilinx Inc. - XC2S100-6PQ208C. The programming environment was Xilinx ISE and the methodology used is "top-down". The module was developed with high-level hardware description language - VHDL. Using software simulator ModelSim and virtual digital analyzer ChipScope made the simulations. |
|Implementation Of a Digital Filtering Algorithm For Rectangular Signals
|(Blagomir Donchev, Stefan Zarev, Marin Hristov)|
| The objective of this project is to demonstrate a particular implementation of filtering of a periodic rectangular pulse signal with a finite spectrum.|
As a result of the implementation, we got a functional system which filters a rectangular pulse signal under a noise impact. The requirement with respect to the noise is that the noise be preliminary determined, i.e. in which part to the spectrum he appears. An advantage of the method is the fact that the amplitude/phase and phase/frequency pulse spectrum recovers with a neglecting small error based on two preliminary chosen and not noised spectral signal constituents.
The implementation is herein presented as a block diagram (Fig. 1). It consists of two main parts: software and hardware. The main points of the frequency spectrum recovery are stated in the software part:
1. Determination of the harmonic constituents by means of a direct Fourier transformation;
2. Recovering of the signal's amplitude/frequency spectrum;
3. Recovering of the signal's phase/frequency spectrum.
The software part contains also a considered opinion about what the hardware part and the system as a whole are expected to be. The hardware part contains a high-level description language definition of a frequency spectrum recovering module. The working algorithm is determined by means of a finite state machine with 5 states. There is a CORDIC algorithm integrated in the design. The arithmetical processing are performed by a sub module implementing a floating point division.
A "Top-Down" design method was carried out which reduced considerably the developing time.
As a basis of the physical implementation, a Xilinx Virtex II FPGA architecture was chosen.
|Analog Lowpass Filter With FPAA Matrix |
|Latest generation of field programmable analog arrays (FPAAs) are highly flexible circuits that exploit inherent precision and versatility of switched-capacitor technology for analog-IC design. The flow is correct by construction, because company's products include software-based functional building blocks, or configurable analog modules, which contain rules for circuit construction and tuning algorithms to realize a given analog functional block using the elements within the FPAAs.
As an example illustrating the application of the methodology for designing by field programmable analog array is proposed a portable tester for automotive engines.
The aim of this development is to be realized a device measuring the rotation speed of automotive engines by vibration sensors.The device transforms the frequency of vibration of the engine by the sensor ADXL105. The low-pass filter is synthesised to extract the useful parts of the signal from the sensor according to the specific of the sensor and the design requirements. The benefits of use of field programmable analog array for the filter realization are increased flexibillity for synthesis and significantly reduced time for the development of the device. As a base for the physical implementation of the filter has been used the dynamically reconfigurable integrated circuit of Anadigm Co, which gives the opportunity for the realization of future adaptable filtration. |
|Lin Protocol Module|
|(Blagomir Donchev, Stefan Zarev, Marin Hristov)|
| The goal of this design is to present an implementation of LIN protocol in programmable logic areas. The physical connection among participants in LIN network is done by LIN transceivers, which make available the communication among all devices in a single common network where there are always one Master Control Unit and up to sixteen Slave Control Units. The basic inner architectures of a master and slave units are the same, as there are specific functions in each one of these two units that has to be fulfilled in design. As an additional function of the module, to reduce the system's power consumption, a LIN node may be sent into the sleep mode without any internal activity and with passive bus driver.|
The basic construct blocks of the developed design are: ContrFSM, LIN_IO, FCB, LIN_Err. The ContrFSM block is a hardware model of a state machine determining the different states in which the device can be set in the process of work. It also accomplishes the communication with the upper layer of LIN ISO model (LLC layer). The LIN_IO executes the interface with LIN network. The main task of LIN_Err block is to identify the situations in which there is a mistake. It is in direct connection with FCB block, which determines the reaction of the system in accordance with the type of the mistake. There are six types of mistakes.
The whole process of development was made with hardware description language VHDL. The "top-down" method has been used in order to decrease the design time.
The presented module meets the requirements of LIN Protocol Specification, Revision 1.2 from November 17, 2000, which is the latest up to now.
|(Boriana Petrova, Nikolai Bankov, Georgy Gegov, Stanislav Markov, Marin Hristov)|
| CAN (Controller Area Network) comprises a complete set of rules for implementing the transfer layer of a serial bus network. BOSCH standardized it as a network protocol in 1985. At first intended to facilitate the "in-car" data communications, today CAN finds its application in a wide variety of network systems where low cost, high speed and increased reliability are important. The Bit Synchronization block includes a so-called digital PLL. It is designed with respect to the CAN synchronization constraints. This block provides the clocks necessary for triggering the state machines of the Frame Processing unit. The method of extracting the clock information from the input bitstream is given as well as the way of eliminating the phase errors and correct sampling of the CAN bus. The logic synthesis is accomplished by Design Compiler Family, one of the Synopsys products based on a VHDL description. By translating of the netlist from Synopsys into CADENCE the components of the cmos24Cells library was substituted with the components from the MIETEC 2 um CMOS library. The simulation is produced by Synopsys VSS Family. The design is checked and the efficiency is guarantied. The layout is designed by Cell Ensemble tool of CADENCE. The total area of the design chip is approximately 8 sq.mm. |
|Digital Circuit for PWM Signals|
|(Peter Goranov, Marin Hristov, Mariana Goranova, Anthony Trifonov)|
|The project has been developed according to needs of smart IC where the sine-wave pulse-width modulated (PWM)
signals are received on its outputs. This set of impulses is used in power electronic circuits for the speed control of the induction motor drives and in the
uninterruptable power supplies. They are known various methods to receive sine-wave PWM signals. The selected method is based on reading of the preliminary written
fixed PWM series in the memory. The design synthesis process involves the following domains: behavioural, structural, and physical representation. The process
consists of the following steps: Natural language synthesis - transformation from a detailed description of the system functions to an algorithmic representation. Algorithmic synthesis - translation from an algorithmic representation to a data flow representation to achieve a designed behaviour. Logic synthesis - translation from data flow representation to a structural logic gate representation. Layout synthesis - translation from logic gate representation to layout representation, i.e. the photo-mask information required by the fabrication process. The synthesis of the integrated circuit is performed using high technologies and software systems. The system is modelled with the high level hardware description language VHDL and subsequently the translation to the schematic level is done with the system for the automated design SYNOPSYS. Checking for errors is done at different levels in the hierarchy by employing multi-level simulation. The digital synthesizer generates an equivalent optimized hardware implementation satisfying the specifications using the CADENCE component library, which provides the basic hardware modules of the final design. Cadence Design Systems provide advanced facilities and CAD resources for design and production of integrated circuits. The synthesis validation is verified subsequently with resimulation of the ready digital system. The used modern methods, tools and programs allow an algorithmic, functional, structural-logical and topological design of the custom integrated circuit so that the received results satisfy completely the required